1. Field of the Invention
This patent specification relates to a differential amplifier circuit, a voltage regulator using the differential amplifier circuit, and a method for controlling the differential amplifier circuit, and more particularly, to a differential amplifier circuit for use in a voltage regulator having low current consumption and capable of quickly switching from a non-operating state to an operating state.
2. Discussion of Related Art
The circuit configuration of voltage regulators is typified into two types: One that consumes a large amount of current to improve power-supply rejection ratio (PSRR) and load transient response, and another that does not have to respond at high speed and thus can reduce current consumption. When a high speed response voltage regulator is employed in, for example, a cellular phone that has an operating mode and a stand-by mode, i.e., a sleep mode, which does not require a high speed response, the current consumption in the stand-by mode results in a great waste.
FIG. 1 is a diagram illustrating an example circuit of a typical voltage regulator 100. The voltage regulator 100 includes a first error amplifier circuit 110 and a second error amplifier circuit 120. The first error amplifier circuit 110 that is required to respond at high speed to fluctuation in an output voltage Vout operates in a high-load operating mode in which the amount of current output from an output terminal 101 is large. The second error amplifier circuit 120 that is not required to respond at high speed to fluctuation in the output voltage Vout operates in a low-load operating mode, in which the amount of current output from the output terminal 101 is small as in a wait state. Control signals are provided by an external controller to select between the first error amplifier circuit 110 and the second error amplifier circuit 120 and control switching of changeover switches SW1, SW2 and SW3. Each of the changeover switches SW1 to SW3 is connected to a point a in the high-load operating mode and is connected to a point b in the low-load operating mode. A reference voltage Vref is applied to the first error amplifier circuit 110 and the second error amplifier circuit 120.
In the high-load operating mode, a bias voltage VA is applied to each gate of NMOS transistors M106 and M107 included in the first error amplifier circuit 110 via the changeover switch SW1. A bias current is supplied to the first error amplifier circuit 110 and the first error amplifier circuit 110 starts operating. On the other hand, since the gate of a NMOS transistor M115 functioning as a bias current generator transistor for the second error amplifier circuit 120 is grounded by the changeover switch SW2 and the NMOS transistor M115 is short-circuited between the gate and the source thereof, a bias current is not generated therein and the second error amplifier circuit 120 stops operating.
In the low-load operating mode, the bias voltage VA is applied to the gate of the NMOS transistor M115 in the second error amplifier circuit 120 via the changeover switch SW2. A bias current is supplied to the second error amplifier circuit 120 and the second error amplifier circuit 120 starts operating. On the other hand, since each gate of the NMOS transistors M106 and M107 functioning as a bias current generator transistor for the first error amplifier circuit 110 is grounded by the changeover switch SW1 and each of the NMOS transistors M106 and M107 is short-circuited between the gate and the source thereof, a bias current is not generated therein and the first error amplifier circuit 110 stops operating. Further, a PMOS transistor M103 that is connected between a power supply voltage VDD and the NMOS transistor M107 is short-circuited between the gate and the source thereof by the changeover switch SW3, which ensures that the first error amplifier circuit 110 stops operating. Thus, the current consumption is reduced in the low-load operating mode, which does not require a high speed response and in which the amount of current is small as in a wait state.
When the operating mode is switched from the low-load operating mode to the high-load operating mode, the changeover switch SW1 is switched from the point b to the point a, the bias voltage VA is applied to each gate of the NMOS transistors M106 and M107, and the bias current begins to be supplied to the first error amplifier circuit 110. However, since each gate of the NMOS transistors M106 and M107 is short-circuited by the changeover switch SW1 until just before the switching, the gate voltage is zero.
A MOS transistor has a gate capacitance between the gate and the source thereof. Therefore, when the changeover switch SW1 is switched from the point b to the point a and the bias voltage VA is applied to each gate of the NMOS transistors M106 and M107, each gate voltage of the NMOS transistors M106 and M107 does not immediately reach the bias voltage VA and it takes time to charge each gate capacitance of the NMOS transistors M106 and M107. Therefore, immediately after the operating mode is switched from the low-load operating mode to the high-load operating mode, the bias current in the first error amplifier circuit 110 is insufficient, which causes the output voltage Vout to drop for a moment. The same problem also occurs when the operating mode is switched from the high-load operating mode to the low-load operating mode.